Integrated circuits contain a plurality of patterned metal lines separated by inter-wiring spacings. Typically, metal patterns of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to a semiconductor substrate. Semiconductor devices of such type, according to current technology, may comprise eight or more metallization layers to satisfy device geometry and micro-miniaturization requirements.
A common process for forming metal lines or plugs is known as “damascene.” Generally, this process involves forming an opening in a dielectric interlayer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After an opening is formed, the opening is filled with copper or copper alloys to form a copper line and possibly a via. Excess metal material on a surface of the dielectric interlayer is then removed by chemical mechanical planarization (CMP).
To accurately control the formation of the opening, an etch stop layer may be used. FIG. 1 illustrates a cross-sectional view of an intermediate stage in the formation of a conventional interconnect structure. Dielectric layer 110 has copper line 112 embedded therein. Etch stop layer (ESL) 114 is formed over dielectric layer 110 and copper line 112. Low-k dielectric layer 120 is formed on ESL 114. Opening 122 is formed in low-k dielectric layer 120. During the formation of opening 122, ESL 114 is used to stop the etching of low-k dielectric layer 120.
In order to reduce the parasitic capacitance in interconnect structures, ESL 114 preferably has a low k value. However, in existing formation processes, the k value of ESL 114 can only be reduced to about 4.0 or greater. The reduction in the k value of ESL 114 may result in the etching selectivity of low-k dielectric layer 120 and ESL 114 to be sacrificed. Further, the reduction in the k value of ESL 114 may result in an increase in leakage in the resulting interconnect structures.